1. Field of the Invention
The present invention relates to a differential amplifier circuit and a drive circuit of a liquid crystal display unit using the same, and more in particular, it relates to improvement of the differential amplifier circuit which is removed from an offset in order to drive a load with a high degree of accuracy.
2. Description of the Prior Art
Heretofore, there has been a problem of the differential amplifier circuit for driving a load developing an output offset because of variation in characteristics of active elements configuring the differential amplifier circuit. To solve this problem, there have been various methods employed so far to correct the output offset. From among those methods, the differential amplifier circuit as disclosed in Japanese Patent Laid-Open No. 9-244590 (patent document 1) is cited as an example of the differential amplifier circuit of a first conventional example having an output offset correcting means using a capacitance.
FIG. 19 is a view showing the differential amplifier circuit of a first conventional example having the output offset correcting means as disclosed in this patent document 1. The differential amplifier circuit of FIG. 19 comprises an operational amplifier circuit 503 and an offset correcting circuit 504. The offset correcting circuit 504 comprises switches 506 and 507 connected in series between a non-inverting input terminal of the operational amplifier circuit 503 and an output terminal 502 of the operational amplifier circuit 503, a capacitor 505 connected between a mutual connecting point of the switches 506 and 507 and an inverting input terminal of the operational amplifier circuit 503, and a switch 508 connected between the inverting input terminal of the operational amplifier circuit 503 and the output terminal 502 of the operational amplifier circuit 503.
FIG. 20 shows an operational timing chart of the differential amplifier circuit of FIG. 19. The operation of the differential amplifier circuit of FIG. 19 will be described below with reference to the timing chart of FIG. 20. First, in the period T1 which is a proceeding state, the switch 507 alone is put into an ON state, and other switches 506 and 508 are put into an OFF state. This allows the output terminal 502 and the inverting input terminal of the operational amplifier circuit 503 to be connected through the capacitor 505. In this state, the preceding output voltage carries over the voltage level of an output voltage Vout.
In the next period T2, in addition to the switch 507, the switch 508 is turned ON. When the voltage level of the input voltage Vin changes, the output voltage Vout changes accordingly, and becomes (Vin+Voff) including an output offset Voff. At this time, the capacitor 505 is short-circuited, and both ends of the capacitor 505 become the same potential. Further, by turning the switches 507 and 508 ON, the both ends of the capacitor 505 are connected to the output terminal 502 of the operational amplifier circuit, and therefore, the potentials of both ends of the capacitor 505 become Vout (=Vin+Voff) by the output of the operational amplifier circuit, respectively.
In the next period T3, while the switch 508 is turned ON as it is, the switch 507 is turned OFF, and after that, the switch 506 is turned ON. This allows one end of the capacitor 505 to be connected to an input terminal 501 and change from Vout to Vin. Since the switch 508 is turned ON, the other terminal of the capacitor 505 remains the output voltage Vout. Hence, the voltage applied to the capacitor 505 becomes as followsVout−Vin=Vin+Voff−Vin=Voffand a charge equivalent to the offset voltage Voff is charged to the capacitor 505.
In the next period T4, the switches 506 and 508 are turned OFF, and after that, the switch 507 is turned ON. By turning the switches 506 and 508 OFF, the capacitor 505 is directly connected between the inverting input terminal and the output terminal 502 of the operational amplifier circuit 503, and the output offset Voff is held by the capacitor 505. By turning the switch 507 ON, the output offset Voff is applied to the inverting input terminal of the operational amplifier circuit 503 with the potential of the output terminal 502 as a reference. As a result, the output voltage Vout becomes as followsVout=Vin+Voff−Voff=Vinand therefore, the output offset is canceled, and a highly precise voltage can be outputted.
Next, as a second conventional example for correcting the output offset, amplifier circuits as disclosed in Japanese Patent Laid-Open Nos. 11-249624 (patent document 2) and 11-305735 (patent document 3) are cited. FIG. 21 is a circuit diagram showing a basic circuit configuration of a low voltage amplifier circuit shown in the patent document 2, and FIG. 22 is a circuit diagram showing the basic circuit configuration of a high voltage amplifier circuit as similarly disclosed in the patent document 2.
The low voltage amplifier circuit shown in FIG. 21 is provided with switching transistors NA1 and NB1 which connects the gate electrode (control electrode) of a P channel (hereinafter, referred to simply as P) MOS transistor PM51 of an input stage to either a (+) input terminal or a (−) input terminal, switching transistors NA2 and NB2 which connects the gate electrode of the PMOS transistor PM52 of the input stage to the (+) input terminal or the (−) input terminal, switching transistors NA3 and NB3 which connects the gate electrode of a N channel (hereinafter, referred to simply as N) MOS transistor NM65 of an output stage to either the drain electrode (second electrode) of the PMOS transistor PM51 of the input stage or the drain electrode of the PMOS transistor PM52 of the input stage, and switching transistors NA4 and NB4 which connects the gate electrodes of the NMOS transistors NM63 and NM64 configuring an active load circuit to either the drain electrode of the PMOS transistor PM51 of the input stage or the drain electrode of the PMOS transistor PM52 of the input stage.
A high voltage amplifier circuit shown in FIG. 22, similarly to the low voltage amplifier circuit shown in FIG. 21, is provided with switching transistors PA1 to PA4 and PB1 to PB4. Here, the gate electrodes of switching transistors NA1 to NA4 and PA1 to PA4 are applied with a control signal A, and the gate electrodes of switching transistors NB1 to NB4 and PB1 to PB4 are applied with a control signal B.
In the low voltage amplifier circuit shown in FIG. 21, a circuit configuration is shown in FIG. 23 where the control signal A is at a H (high) level and the control signal B is at a L level, and a circuit configuration is shown in FIG. 24 where the control signal A is at a L (low) level and the control signal B is at an H level. As evident from these FIGS. 23 and 24, in case of the low voltage amplifier circuit, the MOS transistor of the input stage applied with the input voltage Vin and the MOS transistor of the input stage fed back with the output voltage Vout are exchangeable. Consequently, in the cases of the circuit configuration of FIG. 23 and the circuit configuration of FIG. 24, an output offset is generated in the amplifier circuit where reference numerals are in reverse to one another and the absolute values thereof are equal.
Further, in the high voltage amplifier circuit shown in FIG. 22 also, in the cases of the circuit configuration where the control signal A is at the H level and the control signal B is at the L level and the circuit configuration where the control signal A is at the L level and the control signal B is at the H level, the output offset is generated in the amplifier circuit where reference characters are in reverse to one another and the absolute values thereof are equal.
It is disclosed in the circuit configuration of the patent document 2 that, in an image signal line driving means of the liquid crystal display unit for performing a dot inversion driving, to apply a gradation voltage to a piece of pigment, a high voltage side amplifier circuit for outputting a positive polarity gradation voltage and a low voltage side amplifier circuit for outputting a negative polarity gradation voltage are alternately operated for every frame in response to the polarity, and an operation of alternately changing the MOS transistor of the input stage applied with the input voltage of the amplifier circuit and the MOS transistor of the input stage fed back with the output voltage for every two frames is performed, whereby the output offset generated for each amplifier circuit is equalized for every four frames time-wise. By so doing, the increase and decrease of brightness generated by variation of a voltage applied to the pigment by the output offset is prevented.